During semiconductor device processing, various structures are formed using a variety of materials and technologies. P-channel metal oxide semiconductor (PMOS) devices, n-channel MOS (NMOS) devices, erasable programmable read-only memory (EPROM) devices, resistors, capacitors, etc., can be formed using known processing techniques.
Photolithography is commonly used to form structures such as polysilicon transistor gates (control gates), for example gates for one time programmable (OTP) EPROMs and p-channel and n-channel MOS devices. Due to the very large number of these structures formed with a typical memory device, even a minimal decrease in the width of the control gate can significantly decrease the size of the completed device. Miniaturization of transistor gate “line widths” is, therefore, a particular concern to design engineers. However, the formation of these increasingly narrow control gates across larger substrates using photolithography is becoming ever more difficult. This is particularly true with OTP EPROMs, which have transistor gates which are typically narrower than MOS gates.
When small, closely spaced features are etched at the same time as larger, widely spaced features, it is difficult to complete the etch in the narrow regions without overetching the wide regions. Thus the material in the narrow regions may not be completely removed, or the material in the wide regions may be overetched. This is referred to as the “micro-loading effect.”
Additionally, uneven (non-planar) topography increases the difficulty in clearing conductive materials during an etch, particularly in narrow regions. Uneven topography is especially severe in fabrication of devices using the local oxidation of silicon (LOCOS). FIG. 1 depicts an in-process device formed using a LOCOS process, and comprises the following structures: semiconductor wafer 10 doped to an n-type conductivity; PMOS transistor source region 12 and drain region 14 doped to a p-type conductivity; field isolation (field oxide) 16 formed using a LOCOS process; gate isolation (gate oxide) 18; PMOS transistor gate comprising polysilicon 20 and silicide 22; dielectric spacers 24; interlayer dielectric 26 typically comprising tetraethyl orthosilicate (TEOS) and/or borophosphosilicate glass (BPSG); conductive source contact 28, and; conductive drain contact 30. Various other features can be present in a production device which are not depicted or described for simplicity of explanation.
The FIG. 1 device has been formed successfully. However, due to micro-loading or errors in photolithography, the structures of FIGS. 2 and 3 can result. In the FIG. 2 structure, the transistor gate polysilicon 20 and silicide 22 have not been properly cleared from the drain side during an etch which forms the transistor gate, and the conductive drain contact 30 is shorted to the transistor gate silicide 22 and polysilicon 20. In the FIG. 3 structure, the transistor gate polysilicon 20 and silicide 22 have not been properly cleared from either the drain side or the source side, which results in the shorting of the drain contact 30 to source contact 28 through (and with) the transistor gate silicide 22.
Various test structures are used during semiconductor device fabrication to ensure that the features which are formed are within engineering tolerances and to test for contamination. One structure which is used to test whether features are formed within engineering tolerances is referred to as a “serpentine/comb” structure 40, depicted in FIG. 4. This particular structure comprises a pair of interdigitated “comb” features 42, 44, with an intertwining “serpentine” feature 46 overlying a large doped “moat” region 48. An attempt is made to form this test structure on a test or production wafer, then the test structure can be visually inspected to determine whether the process has been successful. If errors in the serpentine/comb are detected, the manufacturing process may be altered or the wafer may be reworked. This structure is formed to a relatively large size and is used primarily to detect particulate contamination. Thus it has limited success in detecting formation problems resulting from lithography or etching errors in very small polysilicon structures.
There remains a need for additional test tools which reliably determine whether structures formed during device processing are properly formed within engineering tolerances.